ADCs are employed in a variety of applications. In particular, high performance focal plan array (FPA) applications require wide-area coverage, high signal-to-noise-ratios (SNR), high spatial resolution, and high frame rates in various combinations. Conventional FPAs are not particularly well-suited to satisfying combinations of the above requirements. Conventional FPAs typically provide analog readouts, with the analog signals generated at the pixel level converted to digital signals “off chip.” Once converted off-chip, the digital signals may be processed according to the demands of a particular application. Specific analog designs can target (and possibly achieve) one or more requirement, but fail when simultaneously targeting the most aggressive design parameters for imaging applications, such as long-wave infrared imaging (LWIR) applications.
Fundamental limitations on achievable well depth (with concomitant limitations on capacitor size), and the readout noise floor, limit practical scalability of conventional designs. Capacitor size limitations require unnecessarily high frame rates to avoid saturating pixels. Electronics noise and ringing limit the amount of data that can be transmitted on a single output lap to maintain the needed SNR and dynamic range. Attempting to scale conventional analog technology to meet the most demanding requirements leads to a high-power-consumption FPA with many data output taps. This in turn leads to a large, massive, and complex sensor system.
ADCs that are capable of converting a number of signals and a communication structure for manipulating the resulting digital counts in real-time to achieve signal processing functionality, would therefore be highly desirable and may find application in a number of systems, including focal plane arrays.